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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20907-3E
FLASH MEMORY
CMOS
32 M (4M x 8/2M x 16) BIT
MirrorFlashTM*
MBM29PL32TM/BM 90/10
s DESCRIPTION
The MBM29PL32TM/BM is a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes by 8 bits or 2M words by 16 bits. The MBM29PL32TM/BM is offered in 48-pin TSOP(1) and 48-ball FBGA. The device is designed to be programmed in-system with the standard 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued)
s PRODUCT LINE UP
Part No. VCC Max Address Access Time Max CE Access Time Max Page Read Access Time MBM29PL32TM/BM 90 3.0 V to 3.6 V 90 ns 90 ns 25 ns 10 3.0 V to 3.6 V 100 ns 100 ns 30 ns
s PACKAGES
48-pin plastic TSOP (1) 48-ball plastic FBGA
(FPT-48P-M19) * : MirrorFlashTM is a trademark of Fujitsu Limited.
(BGA-48P-M20)
Notes : * Programming in byte mode ( x 8) is prohibited. * Programming to the address that already contains data is prohibited. (It is mandatory to erase data prior to overprogram on the same address.)
MBM29PL32TM/BM90/10
(Continued)
The standard MBM29PL32TM/BM offers access times of 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29PL32TM/BM supports command set compatible with JEDEC single-power-supply EEPROMS standard. Commands are written into the command register. The register contents serve as input to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29PL32TM/BM is programmed by executing the program command sequence. This will invoke the Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase AlgorithmTM which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. All sectors are erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the devices internally return to the read mode. Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The devices electrically erase all bits within a sector simultaneously via hot-hole assisted erase. The words are programmed one word at a time using the EPROM programming mechanism of hot electron injection.
2
MBM29PL32TM/BM90/10
s FEATURES
* 0.23 m Process Technology * Single 3.0 V read, program and erase Minimizes system level power requirements * Industry-standard pinouts 48-pin TSOP (1) (Package suffix: TN - Normal Bend Type) 48-ball FBGA(Package suffix: PBT) * Minimum 100,000 program/erase cycles * High performance Page mode Fast 8 bytes / 4 words access capability * Sector erase architecture Eight 8K byte and sixty-three 64K byte sectors Eight 4K word and sixty-three 32K word sectors Any combination of sectors can be concurrently erased. Also supports full chip erase * Boot Code Sector Architecture T = Top sector B = Bottom sector * HiddenROM 256 bytes / 128 words of HiddenROM, accessible through a "HiddenROM Entry" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC input pin At VIL, allows protection of outermost two 8K bytes / 4K words sectors, regardless of sector protection/unprotection status At VACC, increases program performance * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode * Program Suspend/Resume Suspends the program operation to allow a read in another address * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * Sector Group Protection Hardware method disables any combination of sector groups from program or erase operations * Sector Group Protection Set function by Extended sector protect command * Fast Programming Function by Extended Command * Temporary sector group unprotection Temporary sector group unprotection via the RESET pin This feature allows code changes in previously locked sectors * In accordance with CFI (Common Flash Memory Interface)
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
3
MBM29PL32TM/BM90/10
s PIN ASSIGNMENTS
48-pin Plastic TSOP(1) (Top View) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0
(FPT-48P-M19)
48-ball plastic FBGA (Top View) Marking Side
A6 A13 A5 A9 A4
B6 A12 B5 A8 B4
C6 A14 C5 A10 C4
D6 A15 D5 A11 D4 A19 D3 A20 D2 A5 D1 A1
E6 A16 E5
F6
G6
H6
BYTE DQ15/ VSS A-1 F5 G5 H5
DQ7 DQ14 DQ13 DQ6 E4 F4 G4 VCC G3 H4 DQ4 H3
WE RESET N.C. A3 B3 C3 A18 C2 A6 C1 A2
DQ5 DQ12 E3 F3
RY/BY WP/ ACC A2 A7 A1 A3 B2 A17 B1 A4
DQ2 DQ10 DQ11 DQ3 E2 DQ0 E1 A0 F2 DQ8 F1 CE G2 DQ9 G1 OE H2 DQ1 H1 VSS
(BGA-48P-M20)
4
MBM29PL32TM/BM90/10
s PIN DESCRIPTIONS
MBM29PL32TM/BM Pin Configuration Pin A20 to A0, A-1 DQ15 to DQ0 CE OE WE WP/ACC RESET BYTE RY/BY VCC VSS N.C. Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Hardware Write Protection/Program Acceleration Hardware Reset Pin/Temporary Sector Group Unprotection Select Byte or Word mode Ready/Busy Output Device Power Supply Device Ground No Internal Connection Function
5
MBM29PL32TM/BM90/10
s BLOCK DIAGRAM
DQ15 to DQ0
VCC VSS
Erase Voltage Generator
Input/Output Buffers
WE RESET WP/ACC BYTE
State Control
Command Register
Program Voltage Generator
CE OE
Chip Enable Output Enable Logic
STB
Data Latch
STB
Y-Decoder
Y-Gating
Timer for Program/Erase A20 to A2 A1, A0 (A-1)
Address Latch
X-Decoder
Cell Matrix
s LOGIC SYMBOL
A-1 21 A20 to A0 DQ 15 to DQ 0 CE OE WE WP/ACC RESET 16 or 8
BYTE
RY/BY
6
MBM29PL32TM/BM90/10
s DEVICE BUS OPERATION
MBM29PL32TM/BM User Bus Operations (Word Mode : BYTE = VIH) Operation Standby Autoselect Manufacture Code*1 Autoselect Device Code*1 Read Output Disable Write (Program/Erase) Enable Sector Group Protection*2 Temporary Sector Group Unprotection Reset (Hardware) Sector Write Protection CE OE WE H L L L L L L X X X X L L L H H H X X X X H H H H L L X X X A0 X L H A0 X A0 L X X X A1 X L L A1 X A1 H X X X A2 X L L A2 X A2 L X X X A3 X L L A3 X A3 L X X X A6 X L L A6 X A6 L X X X A9 X VID VID A9 X A9 X X X X DQ0 to DQ15 Hi-Z Code Code DOUT Hi-Z *3 *3 *3 Hi-Z X RESET H H H H H H VID VID L H WP/ ACC X X X X X *4 H H X L
Legend : L = VIL, H = VIH, X = VIL or VIH. See "s ELECTRICAL CHARACTERISTICS 1. DC Characteristics" for voltage levels. Hi-Z = High-Z, VID = 11.5 V to 12.5 V *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See "Sector Group Protection Verify Autoselect Codes". *2 : Refer to "Sector Group Protection" in s FUNCTIONAL DESCRIPTION. *3 : DIN or DOUT as required by command sequence, data pulling, or sector protect algorithm *4 : If WP/ACC = VIL, the outermost two sectors remain protected. If WP/ACC = VIH, the outermost two sectors will be protected or unprotected as determined by the method specified in "Sector Group Protection" in s FUNCTIONAL DESCRIPTION.
7
MBM29PL32TM/BM90/10
MBM29PL32TM/BM User Bus Operations (Byte Mode : BYTE = VIL) Operation Standby Autoselect Manufacture Code*1 Autoselect Device Code*1 Read Output Disable Write (Erase) Enable Sector Group Protection*2 Temporary Sector Group Unprotection Reset (Hardware) Sector Write Protection CE OE WE H L L L L L L X X X X L L L H H H X X X X H H H H L L X X X DQ15/ A0 A-1 X L L A-1 X A-1 L X X X X L H A0 X A0 L X X X A1 X L L A1 X A1 H X X X A2 X L L A2 X A2 L X X X A3 X L L A3 X A3 L X X X A6 A9 X L L A6 X A6 L X X X X VID VID A9 X A9 X X X X DQ0 to WP/ RESET DQ7 ACC Hi-Z Code Code DOUT Hi-Z *3 *3 *3 Hi-Z X H H H H H H VID VID L H X X X X X *4 H H X L
Legend : L = VIL, H = VIH, X = VIL or VIH. See "s ELECTRICAL CHARACTERISTICS 1. DC Characteristics" for voltage levels. Hi-Z = High-Z, VID = 11.5 V to 12.5 V *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See "MBM29PL32TM/BM Standard Command Definitions". *2 : Refer to "Sector Group Protection". *3 : DIN or DOUT as required by command sequence, data pulling, or sector protect algorithm *4 : If WP/ACC = VIL, the outermost two sectors remain protected. If WP/ACC = VIH, the outermost two sectors will be protected or unprotected as determined by the method specified in "Sector Group Protection" in page 23.
8
MBM29PL32TM/BM90/10
MBM29PL32TM/BM Standard Command Definitions*1 Command Sequence Reset*2 Reset*2 Autoselect Program Chip Erase Sector Erase
Word/ Byte Word Byte Word Byte Word Word Byte Word Byte
First Bus Second Bus Third Bus Bus Write Write Cycle Write Cycle Write Cycle Cycles Req'd Addr Data Addr -- 2AAh 555h 2AAh 555h Data -- 55h
Fourth Bus Read/Write Cycle Data --
Fifth Bus Sixth Bus Write Cycle Write Cycle Addr Data Addr Data -- -- -- -- -- -- -- --
Addr Data Addr -- 555h -- F0h --
1 3 3 4 6 6 1 1 3 2 2 20 1 3 4 1 3 4 4
XXXh F0h 555h AAAh 555h AAAh 555h 555h AAAh 555h AAAh AAh
AAAh 555h AAAh 555h 555h AAAh 555h AAAh -- -- 555h AAAh -- -- SA -- 555h
RA*13 RD*13
AAh
55h 55h 55h
90h 00h*13 04h*13 A0h 80h PA 555h AAAh 555h AAAh -- -- -- -- -- SA -- PD AAh
-- -- 2AAh 555h 2AAh 555h -- -- -- -- -- PA --
-- -- 55h
-- -- 555h AAAh SA -- -- -- -- -- WBL --
-- -- 10h
AAh 2AAh AAh 2AAh 555h 2AAh 555h -- -- 2AAh 555h PA
AAh
55h -- -- 55h PD
80h -- -- 20h -- -- 25h --
AAh -- -- -- -- -- 0Fh --
55h -- -- -- -- -- PD --
30h -- -- -- -- -- PD --
Program/Erase Suspend*3 Program/Erase Resume*3 Set to Fast Mode*4 Fast Program*4 Reset from Fast Mode*5 Write to Buffer
Word Byte Word Word/ Byte Word Byte
XXXh B0h XXXh 30h 555h AAAh AAh
XXXh A0h
XXXh 90h XXXh 00h*12 555h AAAh SA 555h AAAh AAh AAh 29h 2AAh 555h -- 2AAh 555h SGA 55h 55h --
Program Buffer to Flash (Confirm) Write to Buffer Abort Reset*6
Extended Sector Group Protection*7,*8
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
AAAh SGA
F0h
-- SGA
--
--
--
--
--
XXXh 60h 55h AAh 555h AAAh 555h AAAh 555h AAAh
60h
40h
*13
--
SD*13
--
--
--
--
Query*9 HiddenROM Entry*10 HiddenROM Program *10,*11 HiddenROM Exit*11
98h
-- 2AAh 555h 2AAh 555h 2AAh 555h
--
-- 555h AAAh 555h AAAh 555h AAAh
--
--
--
--
--
--
AAh
55h
88h
--
--
--
--
--
--
AAh
55h
A0h
PA
PD
--
--
--
--
AAh
55h
90h
XXXh
00h
--
--
--
--
(Continued)
9
MBM29PL32TM/BM90/10
(Continued) Legend : Address bits A20 to A11 = X = "H" or "L" for all address commands except for Program Address (PA), Sector Address (SA) and Sector Group Address (SGA). Bus operations are defined in "MBM29PL32TM/BM User Bus Operations (Word Mode : BYTE = VIH)" and "MBM29PL32TM/BM User Bus Operations (Byte Mode : BYTE = VIL)". RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be programmed / erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13 and A12 will uniquely select any sector. See "Sector Address Table (MBM29PL32TM)" and "Sector Address Table (MBM29PL32BM)". SGA = Sector Group Address to be protected. See "Sector Group Address Table (MBM29PL32TM)" and "Sector Group Address Table (MBM29PL32BM)". RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write plus. WBL = Write Buffer Location HRA = Address of the HiddenROM area ; MBM29PL32TM (Top Boot Type)Word Mode : 1FFF7Fh to 1FFFFFh Byte Mode : 3FFEFFh to 3FFFFFh MBM29PL32BM (Bottom Boot Type)Word Mode : 000000h to 00007Fh Byte Mode : 000000h to 0000FFh
*1 : The command combinations not described in "MBM29PL32TM/BM Standard Command Definitions" are illegal. *2 : Both of these reset commands are equivalent except for "Write to Buffer Abort" reset. *3 : The Erase Suspend and Erase Resume command are valid only during a sector erase operation. *4 : The Set to Fast Mode command is required prior to the Fast Program command. *5 : The Reset from Fast Mode command is required to return to the read mode when the device is in fast mode. *6 : Reset to the read mode. The Write to Buffer Abort Reset command is required after the Write to Buffer operation was aborted. *7 : This command is valid while RESET = VID. *8 : Sector Group Address (SGA) with A6 = 0, A3 = 0, A2 = 0, A1 = 1, and A0 = 0 *9 : The valid address are A6 to A0. *10 : The HiddenROM Entry command is required prior to the HiddenROM programming. *11 : This command is valid during HiddenROM mode. *12 : The data "F0h" is also acceptable. *13 : Indicates read cycle.
10
MBM29PL32TM/BM90/10
Sector Group Protection Verify Autoselect Codes Type Manufacturer's Code Device Code Word Byte Word MBM29PL32TM Extended Device Code*2 MBM29PL32BM Byte Word Byte Word Byte Word Byte Sector Group Protection*4 *1 : A-1 is for Byte mode. *2 : At Word mode, a read cycle at address 01h ( at Byte mode, 02h ) outputs device code. When 227Eh ( at Byte mode, 7Eh ) is output, it indicates that reading two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of 0Eh ( at Byte mode, 1Ch ), as well as at 0Fh ( at Byte mode, 1Eh ). *3 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *4 : Toggle CE, provided SGA = fix and WE = fix. The data in the first cycle is invalid. The data in the second one is valid. A20 to A12 X X X X X X Sector Group Addresses A6 VIL VIL VIL VIL VIL VIL VIL A3 VIL VIL VIH VIH VIH VIH VIL A2 VIL VIL VIH VIH VIH VIH VIL A1 VIL VIL VIH VIH VIH VIH VIH A0 VIL VIH VIL VIH VIL VIH VIL A-1*1 VIL X VIL X VIL X VIL X VIL X VIL VIL Code (HEX) 04h 227Eh 7Eh 221Ah 1Ah 2201h 01h 221Ah 1Ah 2200h 00h *3
11
MBM29PL32TM/BM90/10
Sector Address Table (MBM29PL32TM)
Sector Size Sector (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 Kwords) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) x Address Range 000000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh 0C0000h to 0CFFFFh 0D0000h to 0DFFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh 190000h to 19FFFFh 1A0000h to 1AFFFFh 1B0000h to 1BFFFFh 1C0000h to 1CFFFFh 1D0000h to 1DFFFFh 1E0000h to 1EFFFFh 1F0000h to 1FFFFFh (x16) x Address Range 000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh
(Continued)
12
MBM29PL32TM/BM90/10
Sector Size Sector (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 Kwords) Sector Address SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4
(x8) x Address Range 200000h to 20FFFFh 210000h to 21FFFFh 220000h to 22FFFFh 230000h to 23FFFFh 240000h to 24FFFFh 250000h to 25FFFFh 260000h to 26FFFFh 270000h to 27FFFFh 280000h to 28FFFFh 290000h to 29FFFFh 2A0000h to 2AFFFFh 2B0000h to 2BFFFFh 2C0000h to 2CFFFFh 2D0000h to 2DFFFFh 2E0000h to 2EFFFFh 2F0000h to 2FFFFFh 300000h to 30FFFFh 310000h to 31FFFFh 320000h to 32FFFFh 330000h to 33FFFFh 340000h to 34FFFFh 350000h to 35FFFFh 360000h to 36FFFFh 370000h to 37FFFFh 380000h to 38FFFFh 390000h to 39FFFFh 3A0000h to 3AFFFFh 3B0000h to 3BFFFFh 3C0000h to 3CFFFFh 3D0000h to 3DFFFFh 3E0000h to 3EFFFFh 3F0000h to 3F1FFFh 3F2000h to 3F3FFFh
(x16) x Address Range 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1F8FFFh 1F9000h to 1F9FFFh
(Continued)
13
MBM29PL32TM/BM90/10
(Continued)
Sector Size Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 (Kbytes/ Kwords) Sector Address SA65 SA66 SA67 SA68 SA69 SA70 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 8/4 8/4 8/4 8/4 8/4 8/4 (x8) x Address Range 3F4000h to 3F5FFFh 3F6000h to 3F7FFFh 3F8000h to 3F9FFFh 3FA000h to 3FBFFFh 3FC000h to 3FDFFFh 3FE000h to 3FFFFFh (x16) x Address Range 1FA000h to 1FAFFFh 1FB000h to 1FBFFFh 1FC000h to 1FCFFFh 1FD000h to 1FDFFFh 1FE000h to 1FEFFFh 1FF000h to 1FFFFFh
Note : The address range is A20 to A-1 if in Byte mode (BYTE = VIL) . The address range is A20 to A0 if in Word mode (BYTE = VIH) .
14
MBM29PL32TM/BM90/10
Sector Address Table (MBM29PL32BM)
Sector SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 Sector Size A20 A19 A18 A17 A16 A15 A14 A13 A12 (Kbytes/ Kwords) Sector Address 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) x Address Range 3F0000h to 3FFFFFh 3E0000h to 3EFFFFh 3D0000h to 3DFFFFh 3C0000h to 3CFFFFh 3B0000h to 3BFFFFh 3A0000h to 3AFFFFh 390000h to 39FFFFh 380000h to 38FFFFh 370000h to 37FFFFh 360000h to 36FFFFh 350000h to 35FFFFh 340000h to 34FFFFh 330000h to 33FFFFh 320000h to 32FFFFh 310000h to 31FFFFh 300000h to 30FFFFh 2F0000h to 2FFFFFh 2E0000h to 2EFFFFh 2D0000h to 2DFFFFh 2C0000h to 2CFFFFh 2B0000h to 2BFFFFh 2A0000h to 2AFFFFh 290000h to 29FFFFh 280000h to 28FFFFh 270000h to 27FFFFh 260000h to 26FFFFh 250000h to 25FFFFh 240000h to 24FFFFh 230000h to 23FFFFh 220000h to 22FFFFh 210000h to 21FFFFh 200000h to 20FFFFh 1F0000h to 1FFFFFh (x16) x Address Range 1F8000h to 1FFFFFh 1F0000h to 1F7FFFh 1E8000h to 1EFFFFh 1E0000h to 1E7FFFh 1D8000h to 1DFFFFh 1D0000h to 1D7FFFh 1C8000h to 1CFFFFh 1C0000h to 1C7FFFh 1B8000h to 1BFFFFh 1B0000h to 1B7FFFh 1A8000h to 1AFFFFh 1A0000h to 1A7FFFh 198000h to 19FFFFh 190000h to 197FFFh 188000h to 18FFFFh 180000h to 187FFFh 178000h to 17FFFFh 170000h to 177FFFh 168000h to 16FFFFh 160000h to 167FFFh 158000h to 15FFFFh 150000h to 157FFFh 148000h to 14FFFFh 140000h to 147FFFh 138000h to 13FFFFh 130000h to 137FFFh 128000h to 12FFFFh 120000h to 127FFFh 118000h to 11FFFFh 110000h to 117FFFh 108000h to 10FFFFh 100000h to 107FFFh 0F8000h to 0FFFFFh
(Continued)
15
MBM29PL32TM/BM90/10
Sector Size Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 (Kbytes/ Kwords) Sector Address SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4
(x8) x Address Range 1E0000h to 1EFFFFh 1D0000h to 1DFFFFh 1C0000h to 1CFFFFh 1B0000h to 1BFFFFh 1A0000h to 1AFFFFh 190000h to 19FFFFh 180000h to 18FFFFh 170000h to 17FFFFh 160000h to 16FFFFh 150000h to 15FFFFh 140000h to 14FFFFh 130000h to 13FFFFh 120000h to 12FFFFh 110000h to 11FFFFh 100000h to 10FFFFh 0F0000h to 0FFFFFh 0E0000h to 0EFFFFh 0D0000h to 0DFFFFh 0C0000h to 0CFFFFh 0B0000h to 0BFFFFh 0A0000h to 0AFFFFh 090000h to 09FFFFh 080000h to 08FFFFh 070000h to 07FFFFh 060000h to 06FFFFh 050000h to 05FFFFh 040000h to 04FFFFh 030000h to 03FFFFh 020000h to 02FFFFh 010000h to 01FFFFh 00E000h to 00FFFFh 00C000h to 00DFFFh 00A000h to 00BFFFh
(x16) x Address Range 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh
(Continued)
16
MBM29PL32TM/BM90/10
(Continued)
Sector Size Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 (Kbytes/ Kwords) Sector Address SA4 SA3 SA2 SA1 SA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 8/4 8/4 8/4 8/4 8/4 (x8) x Address Range 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh (x16) x Address Range 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh
Note : The address range is A20 to A-1 if in Byte mode (BYTE = VIL) . The address range is A20 to A0 if in Word mode (BYTE = VIH) .
17
MBM29PL32TM/BM90/10
Sector Group Address Table (MBM29PL32TM) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 A20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 A16 X X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 X X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 X X X SA60 to SA62 A14 X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X Sectors SA0 to SA3 SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA28 to SA31 SA32 to SA35 SA36 to SA39 SA40 to SA43 SA44 to SA47 SA48 to SA51 SA52 to SA55 SA56 to SA59
18
MBM29PL32TM/BM90/10
Sector Group Address Table (MBM29PL32BM) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A17 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X X A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 X X X SA8 to SA10 A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
19
MBM29PL32TM/BM90/10
Common Flash Memory Interface Code A6 to A0 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh DQ15 to DQ0 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0027h Description Query-unique ASCII string "QRY" Primary OEM Command Set (02h = Fujitsu standard) Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table (00h = not applicable) VCC Min (write/erase) DQ7 to DQ4: 1 V/bit, DQ3 to DQ0: 100 mV/bit VCC Max (write/erase) DQ7 to DQ4: 1 V/bit, DQ3 to DQ0: 100 mV/bit VPP Min voltage (00h = no Vpp pin) VPP Max voltage (00h =no Vpp pin) Typical timeout per single write 2N s Typical timeout for Min size buffer write 2N s Typical timeout per individual sector erase 2N ms Typical timeout for full chip erase 2N ms Max timeout for write 2N times typical Max timeout for buffer write 2N times typical Max timeout per individual sector erase 2N times typical Max timeout for full chip erase 2N times typical Device Size = 2N byte Flash Device Interface description 02h : x 8/ x 16 Max number of byte in multi-byte write = 2N Number of Erase Block Regions within device (02h = Boot)
1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h
0036h 0000h 0000h 0007h 0007h 000Ah 0000h 0001h 0005h 0004h 0000h 0016h 0002h 0000h 0005h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h
Erase Block Region 1 Information
Erase Block Region 2 Information
(Continued)
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MBM29PL32TM/BM90/10
(Continued) A6 to A0
35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch
DQ15 to DQ0 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0050h 0052h 0049h 0031h 0033h 0008h 0002h 0004h 0001h 0004h 0000h 0000h 0001h
Description
Erase Block Region 3 Information
Erase Block Region 4 Information
Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock Required Erase Suspend (02h = To Read & Write) Number of sectors in per group Sector Temporary Unprotection (01h = Supported) Sector Protection Algorithm Dual Operation (00h = Not Supported) Burst Mode Type (00h = Not Supported) Page Mode Type (01h = 4-Word Page Supported) VACC (Acceleration) Supply Minimum DQ7 to DQ4: 1 V/bit, DQ3 to DQ0: 100 mV/bit VACC (Acceleration) Supply Maximum DQ7 to DQ4: 1 V/bit, DQ3 to DQ0: 100 mV/bit CFI Write Protect (02h = Bottom Boot Device with WP Protect 03h = Top Boot Device with WP Protect) Program Suspend (01h = Supported)
4Dh
00B5h
4Eh
00C5h
4Fh
00XXh
50h
01h
21
MBM29PL32TM/BM90/10
s FUNCTIONAL DESCRIPTION
Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and the other via the RESET pin only. When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC 0.3 V. Under this condition the current consumed is less than 5 A Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even when CE = "H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L") . Under this condition the current consumed is less than 5 A Max. Once the RESET pin is set high, the device requires tRH as a wake-up time for output to be valid for read access. During standby mode, the output is in the high impedance state, regardless of OE input. Automatic Sleep Mode Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in applications such as handy terminal, which requires low power consumption. To activate this mode, the device automatically switch themselves to low power mode when the device addresses remain stable after tACC + 30 ns from data valid. It is not necessary to control CE, WE, and OE in this mode. The current consumed is typically 1 A (CMOS Level). Since the data are latched during this mode, the data are continuously read out. When the addresses are changed, the mode is automatically canceled and the device read-out the data for changed addresses. Autoselect The Autoselect mode allows reading out of a binary code and identifies its manufacturer and type.It is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. To activate this mode, the programming equipment must force VID on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling A0. All addresses can be either High or Low except A6, A3,A2,A1 and A0. See "MBM29PL32TM/BM User Bus Operations (Word Mode : BYTE = VIH)" and "MBM29PL32TM/BM User Bus Operations (Byte Mode : BYTE = VIL)" in sDEVICE BUS OPERATION. The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "MBM29PL32TM/BM Standard Command Definitions" in sDEVICE BUS OPERATION.Refer to Autoselect Command section. In Word mode, a read cycle from address 00h returns the manufacturer's code (Fujitsu = 04h) . A read cycle at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at addresses of 0Eh and 0Fh. Notice that the above applies to Word mode. The addresses and codes differ from those of Byte mode. Refer to "Sector Group Protection Verify Autoselect Codes" in sDEVICE BUS OPERATION. Read Mode The device has two control functions required to obtain data at the outputs. CE is the power control and used for a device selection. OE is the output control and used to gate data to the output pins. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, input hardware reset or to change CE pin from "H" or "L".
22
MBM29PL32TM/BM90/10
Page Mode Read The device is capable of fast read access for random locations within limited address location called Page. The Page size of the device is 8 bytes / 4 words, within the appropriate Page being selected by the higher address bits A20 to A2 and the address bits A1 to A0 in Word mode ( A1 to A-1 in Byte mode) determining the specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The initial page access is equal to the random access (tACC) and subsequent Page read access (as long as the locations specified by the microprocessor fall within that Page) is equivalent to the page address access time (tPACC). Here again, CE selects the device and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast Page mode, accesses are obtained by keeping A20 to A2 constant and changing A1 and A0 in Word mode ( A1 to A-1 in Byte mode ) to select the specific word within that Page. Output Disable With the OE input at logic high level (VIH), output from the devices are disabled. This may cause the output pins to be in a high impedance state. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the device function. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE, whichever starts first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Group Protection The device features hardware sector group protection. This feature will disable both program and erase operations in any combination of thirty two sector groups of memory.See "Sector Group Address Table (MBM29PL32TM)" and "Sector Group Address Table (MBM29PL32BM)" in sDEVICE BUS OPERATION. The user`s side can use the sector group protection using programming equipment. The device is shipped with all sector groups that are unprotected. To activate it, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL and A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. "Sector Address Table (MBM29PL32TM)" and "Sector Address Table (MBM29PL32BM)" in sDEVICE BUS OPERATION defines the sector address for each of the seventy-one (71) individual sectors, and "Sector Group Address Table (MBM29PL32TM)" and "Sector Group Address Table (MBM29PL32BM)" in sDEVICE BUS OPERATION defines the sector group address for each of the twenty-four (24) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See "Sector Group Protection Timing Diagram" in sSWITCHING WAVEFORMS and "Sector Group Protection Algorithm" in sFLOW CHART for sector group protection timing diagram and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical "1" code at device output DQ0 for a protected sector. Otherwise the device will produce "0" for unprotected sectors. In this mode, the lower order addresses, except for A0, A1, A2, A3, and A6 can be either High or Low. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires applying to VIL on Byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses(A20, A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical "1" at DQ0 for a protected sector group. See "Sector Group Protection Verify Autoselect Codes" in sDEVICE BUS OPERATION for Autoselect codes. 23
MBM29PL32TM/BM90/10
Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to "Temporary Sector Group Unprotection Timing Diagram" in sSWITCHING WAVEFORMS and "Temporary Sector Group Unprotection Algorithm" in sFLOW CHART. Hardware Reset The devices may be reset by driving the RESET pin to VIL from VIH. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode "tREADY" after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional "tRH" before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Write Protect (WP) The Write Protection function provides a hardware method of protecting certain outermost 8K bytes / 4K words sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the outermost 8K bytes / 4K words sectors independently of whether this sector was protected or unprotected using the method described in "Sector Group Protection" above. If the system asserts VIH on the WP/ACC pin, the device reverts of whether the outermost 8K bytes / 4K words sectors were last set to be protected to the unprotected status. Sector protection or unprotection for this sector depends on whether this was last protected or unprotected using the method described in "Sector protection/ unprotection". Accelerated Program Operation The device offers accelerated program operation which enables programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 85%. This function is primarily intended to allow high speed programing, so caution is needed as the sector group becomes temporarily unprotected. The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device is automatically set to fast mode. Therefore, the present sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from the WP/ ACC pin while programming. See "Accelerated Program Timing Diagram" in sSWITCHING WAVEFORM.
24
MBM29PL32TM/BM90/10
s COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. "MBM29PL32TM/BM Standard Command Definitions" in sDEVICE BUS OPERATION shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress.Moreover Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands must be asserted to DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read mode, the Reset operation is initiated by writing the Reset command sequence into the command register. The devices remain enabled for reads until the command register contents are altered. The devices will automatically be in the reset state after power-up. In this case, a command sequence is not required in order to read data. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However applying high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be read from the address, and an actual data of memory cell can be read from the another address. Following the command write, a read cycle from address 00h returns the manufactures's code (Fujitsu = 04h). A read cycle at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at address of 0Eh as well as at 0Fh. Notice that above applies to Word mode. The addresses and codes differ from those of Byte mode. Refer to "Sector Group Protection Verify Autoselect Codes" in sDEVICE BUS OPERATION. To terminate the operation, it is necessary to write the Reset command into the register. To execute the Autoselect command during the operation, Reset command must be written before the Autoselect command. Programming The devices are programmed on a word-by-word basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) starts programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit) or RY/BY. The Data Polling and Toggle Bit are automatically performed at the memory location being programmed. The programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which the devices return to the read mode and plogram addresses are no longer latched. Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance. Hence Data Polling requires the same address which is being programmed. If hardware reset occurs during the programming operation, the data being written is not guaranteed. 25
MBM29PL32TM/BM90/10
Programming is allowed in any address sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may result in either failure condition or an apparent success according to the data polling algorithm. But a read from Reset mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Note that attempting to program a "1" over a "0" will result in programming failure. This precaution is the same with Fujitsu standard NOR devices. "Embedded ProgramTM Algorithm" in sFLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Program Suspend/Resume The Program Suspend command allows the system to interrupt a program operation so that data can be read from any address. Writing the Program Suspend command (B0h) during Embedded Program operation immediately suspends the programming. When the Program Suspend command is written during a programming process, the device halts the program operation within 1us and updates the status bits.After the program operation has been suspended, the system can read data from any address. The data at program-suspended address is not valid. Normal read timing and command definitions apply. After the Program Resume command (30h) is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. When issuing program suspend command in 4 s after issuing program command, determine the status of program operation by reading status bit at more 4 s after issuing program resume command. The system also writes the Autoselect command sequence in the Program Suspend mode. The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. When the device exits the Autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Program Resume command to exit from the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device resumes programming. Do not read CFI code after HiddenROM Entry and Exit in program suspend mode. Write Buffer Programming Operations Write Buffer Programming allows the system write to series of 16 words in one programming operation. This results in faster effective word programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle selecting the Sector Address in which programming will occur. In forth cycle contains both Sector Address and unique code for data bus width will be loaded into the page buffer at the Sector Address in which programming will occur. The system then writes the starting address/data combination. This "starting address" must be the same Sector Address used in third and fourth cycles and its lower addresses of A3 to A0 should be 0h. All subsequent address must be incremented by 1. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) starts programming. Upon executing the Write Buffer Programming Operations command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. DQ7(Data Polling), DQ6(Toggle Bit), DQ5(Exceeded Timing Limits), DQ1(Write-to-Buffer Abort) should be monitored to determine the device status during Write Buffer Programming. In addition to these functions, it is also possible to indicate to the host system that Write Buffer Programming Operations are either in progress or have been completed by RY/BY. See "Hardware Sequence Flags". The Data polling techniques described in "Data Polling Algorithm" in sFLOW CHART should be used while monitoring the last address location loaded into the write buffer. In addition, it is not neccessary to specify an 26
MBM29PL32TM/BM90/10
address in Toggle Bit techniques described in "Toggle Bit Algorithm" in sFLOW CHART. The automatic programing operation is completed when the data on DQ7 is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched ( See "Hardware Sequence Flags"). The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Once the write buffer programming is set, the system must then write the "Program Buffer to Flash" command at the Sector Address. Any other address/data combination will abort the Write Buffer Programming operation and the device will continue busy state. The Write Buffer Programming Sequence can be ABORTED by doing the following : * Different Sector Address is asserted. * Write data other than the "Program Buffer to Flash" command after the specified number of "data load" cycles. A "Write-to-Buffer-Abort Reset" command sequence must be written to the device to return to read mode. (See "MBM29PL32TM/BM Standard Command Definitions" in sDEVICE BUS OPERATION for details on this command sequence.) Chip Erase Chip erase is a six bus cycle operation. It begins two "unlock" write cycles followed by writing the "set-up" command, and two "unlock" write cycles followed by the chip erase command which invokes the Embedded Erase algorithm. The device does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm the devices automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The system can determine the erase operation status by using DQ7 (Data Polling), DQ6 (Toggle Bit I) and DQ2 (Toggle Bit II) or RY/BY output signal. The chip erase begins on the rising edge of the last CE or WE, whichever happens first from last command sequence and completes when the data on DQ7 is "1" (See Write Operation Status section.) at which time the device returns to read mode. Sector Erase Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. Multiple sectors may be erased concurrently by writing the same six bus cycle operations. This sequence is followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than Erase Time-out time(tTOW). Otherwise that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the "tTOW" timeout window the timer is reset (monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer). Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete (refer to the Write Operation Status). Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70). Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase using the Embedded Erase Algorithm. When erasing a sector, the remaining unselected sectors remain unaffected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit) or
RY/BY.
The sector erase begins after the "tTOW" time-out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and completes when the data on DQ7 is "1" (see Write Operation Status section), at which the devices return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. 27
MBM29PL32TM/BM90/10
Erase Suspend/Resume The Erase Suspend command allows the user to interrupt Sector Erase operation and then perform read or programming to a sector not being erased. This command is applicable ONLY during the Sector Erase operation within the time-out period for sector erase. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the "Erase Resume" command (30h) resumes the erase operation. When the "Erase Suspend" command is written during the Sector Erase operation, the device takes maximum of "tSPD" to suspend the erase operation. When the devices enter the erase-suspended mode, the RY/BY output pin will be at High-Z and the DQ7 bit will be at logic "1" and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Do not issue program command after entering erase-suspend-read mode. Fast Mode Set/Reset The device has Fast Mode function. It dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming consists of two cycles instead of four bus cycles in standard program command. The read operation is also executed after exiting this mode. During the Fast mode, do not write any command other than the Fast program/Fast mode reset command. To exit from this mode, write Fast Mode Reset command into the command register. (Refer to the "Embedded ProgramTM Algorithm for Fast Mode" in sFLOW CHART.) The VCC active current is required even CE = VIH during Fast Mode. Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). See "Embedded ProgramTM Algorithm for Fast Mode" in sFLOW CHART. Extended Sector Group Protection In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables protection of the sector group by forcing VID on RESET pin and writes a command sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set VIL for the other addresses pins is recommended), and write extended sector group protection command (60h). A sector group is typically protected in 250 s. To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a command (40h). Following the command write, a logical "1" at device output DQ0 will produce for protected sector in the read operation. If the output data is logical "0", write the extended sector group protection command (60h) again. To terminate the operation, set RESET pin to VIH. (Refer to the "Extended Sector Group Protection Timing Diagram" in sSWITCHING WAVEFORMS and "Extended Sector Group Protection Algorithm" in sFLOW CHART.)
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MBM29PL32TM/BM90/10
Query Command (CFI : Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ15 to DQ8) is "0". Refer to the CFI code table. To terminate operation, it is necessary to write the Reset command sequence into the register. (See "Common Flash Memory Interface Code" in sDEVICE BUS OPERATION.) HiddenROM Mode (1) HiddenROM Region The HiddenROM (HiddenROM) feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The HiddenROM region is 256 bytes / 128 words in length. After the system writes the HiddenROM Entry command sequence, it may read the HiddenROM region by using device addresses A6 to A0 (A20 to A7 are all "0"). That is, the device sends only program command that would normally be sent to the address to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the address. If you request Fujitsu to program the ESN in the device, please contact a Fujitsu representative for more information. (2) HiddenROM Entry Command The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Programming is allowed in this area until it is protected. However, once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required. The HiddenROM area is 256 bytes / 128 words. This area is in SA0 . Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM mode when the HiddenROM area appears. Sectors other than the block area SA0 can be read during HiddenROM mode. Read/program of the HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. Note that any other commands should not be issued than the HiddenROM program/protection/reset commands during the HiddenROM mode. When you issue the other commands including the suspend resume capability, send the HiddenROM reset command first to exit the HiddenROM mode and then issue each command.
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MBM29PL32TM/BM90/10
(3) HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the usual program command, except that it needs to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data pooling, DQ6 Toggle bit or RY/BY. You should pay attention to the address to be programmed. If an address not in the HiddenROM area is selected, the previous data will be deleted. During the write into the HiddenROM region, the program suspend command issuance is prohibited. (4) HiddenROM Protect Command There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command (60h) , set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and write the sector group protect command (60h) during the HiddenROM mode. The same command sequence may be used because it is the same as the extension sector group protect in the past, except that it is in the HiddenROM mode and does not apply high voltage to the RESET pin. Please refer to above mentioned "Extended Sector Group Protection" for details of sector group protect setting. The other method is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address in the HiddenROM area, and read. When "1" appears on DQ0, the protect setting is completed. "0" will appear on DQ0 if it is not protected. Apply write pulse again. The same command sequence could be used for the above method because other than the HiddenROM mode, it is the same as the sector group protect previously mentioned. Take note that other sector groups will be affected if an address other than those for the HiddenROM area is selected for the sector group address, so please be careful. Pay close attention that once it is protected, protection CANNOT BE CANCELLED.
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MBM29PL32TM/BM90/10
Write Operation Status Detailed in "Hardware Sequence Flags" are all the status flags which can determine the status of the device for current mode operation. When checking Hardware Sequence Flags during program operations, it should be checked 4 s after issuing program command. During sector erase, the part provides the status flags automatically to the I/O ports. The information on DQ2 is address sensitive. If an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which sectors are erasing. Once erase suspend is entered address sensitivity still applies. If the address of a non-erasing sector (one available for read) is provided, then stored data can be read from the device. If the address of an erasing sector (one unavailable for read) is applied, the device will output its status bits. Hardware Sequence Flags Status Embedded Program Algorithm Embedded Erase Algorithm Program Suspend Mode Program-Suspend-Read (Program Suspended Sector) Program-Suspend-Read (Non-Program Suspended Sector) Erase-Suspend-Read (Erase Suspended Sector) Erase Suspend Mode Erase-Suspend-Read (Non-Erase Suspended Sector) Erase-Suspend-Program (Non-Erase Suspended Sector) Embedded Program Algorithm Exceeded Embedded Erase Algorithm Time Erase Erase-Suspend-Program Limits Suspend (Non-Erase Suspended Sector) Mode BUSY State Write to Buffer*4 Exceeded Timing Limits ABORT State DQ7 DQ7 0 Data Data 1 Data DQ7 DQ7 0 DQ7 DQ7 DQ7 N/A DQ6 Toggle Toggle Data Data 1 Data Toggle Toggle Toggle Toggle Toggle Toggle Toggle DQ5 0 0 Data Data 0 Data 0 1 1 1 0 1 0 DQ3 0 1 Data Data 0 Data 0 0 1 0 N/A N/A N/A DQ2 1 Toggle*1 Data Data Toggle*1 Data 1*2 1 N/A N/A N/A N/A N/A DQ1*3 0 N/A Data Data N/A Data N/A N/A N/A N/A 0 0 1
In Progress
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2 : Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. *3 : DQ1 indicates the Write-to-Buffer ABORT status during Write-Buffer-Programming operations. *4 : The Data Polling algorithm detailed in "Data Polling Algorithm" in sFLOW CHART should be used for WriteBuffer-Programming operations. Note that DQ7 during Write-Buffer-Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
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MBM29PL32TM/BM90/10
DQ7 Data Polling The devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read devices will produce reverse data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in "Data Polling Algorithm" in sFLOW CHART. For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors. Otherwise, the status may become invalid. If a program address falls within a protected sector, Data polling on DQ7 is active for approximately 1 s, then the device returns to read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 100 s, then the device returns to read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time, and then that byte's valid data the next. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device completes the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may still be invalid. The valid data on DQ7 to DQ0 will be read on the successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erace Suspendmode or sector erase time-out. See "Data Polling during Embedded Algorithm Operation Timing Diagram" in sSWITCHING WAVEFORM for the Data Polling timing specifications and diagram. DQ6 Toggle Bit I The device also feature the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequences. The Toggle Bit I is active during the sector time out. In programm operation, if the sector being written to is protected, the Toggle bit will toggle for about 1 s and then stop toggling with the data unchanged. In erase, the device will erase all the selected sectors except for the protected ones. If all selected sectors are protected, the chip will toggle the Toggle bit for about 100 s and then drop back into read mode, having data kept remained. Either CE or OE toggling will cause the DQ6 to toggle. See " Toggle Bit l Timing Diagramduring Embedded Algorithm Operations" in sSWITCHING WAVEFORM for the Toggle Bit I timing specifications and diagram.
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MBM29PL32TM/BM90/10
DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition indicating that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in "MBM29PL32TM/BM User Bus Operations (Word Mode : BYTE = VIH)" and "MBM29PL32TM/BM User Bus Operations (Byte Mode : BYTE = VIL)" in sDEVICE BUS OPERATION. The DQ5 failure condition may also appear if a user tries to program a non blank location without pre-erase. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a "1". Note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device with command sequence. DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates a valid erase command has been written, DQ3 may be used to determine whether the sector erase timer window is still open. If DQ3 is "1" the internally controlled erase cycle has begun. If DQ3 is "0", the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See "Hardware Sequence Flags". DQ2 Toggle Bit II This Toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also "Hardware Sequence Flags" and "DQ2 vs. DQ6" in sSWITCHING WAVEFORM. Furthermore, DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles if this bit is read from an erasing sector.
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MBM29PL32TM/BM90/10
Reading Toggle Bits DQ6 / DQ2 Whenever the system initially begins reading Toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a Toggle bit is toggling. Typically a system would note and store the value of the Toggle bit after the first read. After the second read, the system would compare the new value of the Toggle bit with the first. If the Toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if, after the initial two read cycles, the system determines that the Toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then determine again whether the Toggle bit is toggling, since the Toggle bit may have stopped toggling just as DQ5 went high. If the Toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the Toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the Toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to "Toggle Bit Algorithm" in sFLOW CHART.) Toggle Bit Status Mode Program Erase Erase-Suspend-Read (Erase-Suspended Sector) Erase-Suspend-Program DQ7 DQ7 0 1 DQ7 DQ6 Toggle Toggle 1 Toggle DQ2 1 Toggle *1 Toggle *1 1 *2
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2 : Reading from the non-erase suspend sector address will indicate logic "1" at the DQ2 bit. DQ1 Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See "Write Buffer Programming Operations" section for more details. RY/BY Ready/Busy The device provides a RY/BY open-drain output pin to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. If the device is placed in an Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pullup resister to VCC. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. See "RY/BY Timing Diagram during Program/Erase Operation Timing Diagram" and "RESET Timing Diagram ( During Embedded Algorithms )" in sSWITCHING WAVEFORM for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. 34
MBM29PL32TM/BM90/10
Word/Byte Configuration BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the device operates in the word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. In this mode, DQ15/A-1 pin becomes the lowest address bit, and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically reset the internal state machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. (1) Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO. If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid. (2) Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. (3) Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must be a logical zero while OE is a logical one. (4) Power-up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up. (5) Sector Protection Device user is able to protect each sector group individually to store and protect data. Protection circuit voids both write and erase commands that are addressed to protected sectors. Any commands to write or erase addressed to protected sector are ignored .
35
MBM29PL32TM/BM90/10
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All Pins Except A9, OE, and RESET *1,*2 Power Supply Voltage *1 Input Voltage A9, OE, and RESET * * Input Voltage WP/ACC *1,*3
1, 3
Symbol Tstg TA VIN, VOUT VCC VIN VACC
Rating Min -55 -20 -0.5 -0.5 -0.5 -0.5 Max +125 +85 VCC +0.5 +4.0 +12.5 +12.5
Unit C C V V V V
*1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -0.2 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns *3 : Minimum DC input voltage is -0.5V. During voltage transitions, these pins may undershoot VSS to -0.2 V for periods of up to 20 ns.Voltage difference between input and supply voltage ( VIN-VCC) dose not exceed to +9.0 V. Maximum DC input voltage is +12.5 V which may overshoot to +14.0 V for periods of up to 20 ns . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature VCC Supply Voltage * * : Voltage is defined on the basis of VSS = GND = 0V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 90 10 Symbol TA VCC Value Min -20 -20 +3.0 Max +70 +85 +3.6 Unit C V
36
MBM29PL32TM/BM90/10
s MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
+0.6 V -0.5 V -2.0 V
20 ns
20 ns
20 ns
Maximum Undershoot Waveform
20 ns
VCC +2.0 V VCC +0.5 V 0.7 x VCC
20 ns 20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V +12.5 V VCC +0.5 V
20 ns 20 ns
Note: This waveform is applied for A9, OE, RESET, and ACC.
Maximum Overshoot Waveform 2
37
MBM29PL32TM/BM90/10
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current VCC Active Current (Read ) *1,*2 VCC Active Current (Intra-Page Read ) *2 VCC Active Current (Program / Erase) *2,*3 VCC Standby Current *2 VCC Reset Current *2 Symbol ILI ILO ILIT Conditions VIN = VSS to VCC, VCC = VCC Max WP/ACC pin Others Value Min -2.0 -1.0 -1.0 -- -- -- -- -- -- -- -- -- Typ -- -- -- -- 18 16 35 35 10 50 1 1 Max +2.0 +1.0 +1.0 35 20 20 50 50 20 60 5 5 mA mA A A mA Unit A A A
VOUT = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9, OE, RESET = 12.5 V CE = VIL, OE = VIH, Word f = 5 MHz Byte CE = VIL, OE = VIH, Word f = 10 MHz Byte CE = VIL, OE = VIH, tPRC = 25ns, 4-Word CE = VIL, OE = VIH CE = VCC 0.3 V, RESET = VCC 0.3 V, OE = VIH, WP/ACC = VCC 0.3 V RESET = VCC 0.3 V, WP/ACC = VCC 0.3 V CE = VSS 0.3 V, RESET = VCC 0.3 V, VIN = VCC 0.3V or Vss 0.3V, WP/ACC = VCC 0.3 V CE = VIL, OE = VIH CE = VIL, OE = VIH, WP/ACC pin Vcc = Vcc Max, WP/ACC =VACC Vcc Pin Max -- -- VCC = 3.0 V to 3.6 V VCC = 3.0 V to 3.6 V IOL = 4.0 mA, VCC = VCC Min IOH = -2.0 mA, VCC = VCC Min --
ICC1
ICC2 ICC3 ICC4 ICC5
VCC Automatic Sleep Current *4 VCC Active Current (Erase-Suspend-Program) *2 ACC Accelerated Program Current Input Low Level Input High Level Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration Voltage for Autoselect, and Temporary Sector Unprotected Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage
ICC6
--
1
5
A
ICC7
-- -- -- -0.5 0.7xVCC 11.5 11.5 -- 0.85xVCC 2.3
50 -- -- -- -- 12.0 12.0 -- -- --
60 20 60 0.6 VCC + 0.3 12.5 12.5 0.45 -- 2.5
mA
IACC VIL VIH VACC VID VOL VOH VLKO
mA V V V V V V V
*1 : The lCC current listed includes both the DC operating current and the frequency dependent component. *2 : Maximum ICC values are tested with VCC = VCC Max *3 : ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress. *4 : Automatic sleep mode enables the low power mode when address remain stable for tACC + 30 ns. 38
MBM29PL32TM/BM90/10
2. AC Characteristics
* Read Only Operations Characteristics Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Page Read Cycle Time Page Address to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable Read Hold Time Toggle and Data Polling Output Enable to Output High-Z Output Hold Time From Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode Symbols JEDEC Standard tAVAV tAVQV tELQV -- -- tGLQV tEHQZ -- tGHQZ tAXQX -- tRC tACC tCE tPRC tPACC tOE tDF tOEH tDF tOH tREADY -- CE = VIL, OE = VIL OE = VIL -- CE = VIL, OE = VIL -- -- -- -- -- -- -- Value* Condition Min 90 25 0 10 0 90 Max 90 90 25 25 25 25 20 Min 100 30 0 10 0 10 Max 100 100 30 30 30 30 20 ns ns ns ns ns ns ns ns ns ns ns s Unit
* : Test Conditions : Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCC Timing measurement reference level Input : VCC / 2 Output : VCC / 2
3.3 V Diode = 1N3064 or Equivalent Device Under Test 6.2 k CL Diode = 1N3064 or Equivalent
2.7 k
Test Conditions
39
MBM29PL32TM/BM90/10
* Write (Erase/Program) Operations Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Data Setup Time Data Hold Time OE Setup Time CE High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE High to WE Low) Read Recover Time Before Write (OE High to CE Low) CE Setup Time WE Setup Time CE Hold Time WE Hold Time CE Pulse Width Write Pulse Width CE Pulse Width High Write Pulse Width High Effective Page Programming Time Per Word (Write Buffer Programming) Programming Time Sector Erase Operation * VCC Setup Time Recovery Time From RY/BY Erase/Program Valid to RY/BY Delay Rise Time to VID *
2 1
Symbol JEDEC Standard tAVAV tAVWL -- tWLAX -- tDVWH tWHDX -- -- -- tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tELEH tWLWH tEHEL tWHWL tWC tAS tASO tAH tAHT tDS tDH tOES tCEPH tOEPH tGHWL tGHEL tCS tWS tCH tWH tCP tWP tCPH tWPH Min 90 0 15 45 0 35 0 0 20 20 0 0 0 0 0 0 35 35 25 30 tWHWH2 -- -- -- -- -- -- tWHWH2 tVCS tPB tBUSY tVIDR tVACCR tVLHT 50 0 500 500 4
Value 90 Typ 23.5 100 1.0 Max 90 Min 100 0 15 45 0 35 0 0 20 20 0 0 0 0 0 0 35 35 25 30 50 0 500 500 4 23.5 100 1.0 90 10 Typ Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s ns ns ns ns s Unit
tWHWH1
tWHWH1
Word
Rise Time to VACC *3 Voltage Transition Time *2
(Continued)
40
MBM29PL32TM/BM90/10
(Continued)
Parameter Write Pulse Width *2 OE Setup Time to WE Active * CE Setup Time to WE Active * RESET Pulse Width RESET High Time Before Read Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time
2 2
Symbol JEDEC Standard -- -- -- -- -- -- -- -- tWPP tOESP tCSP tRP tRH tEOE tTOW tSPD Min 100 4 4 500 100 50
Value 90 Typ Max 90 20 Min 100 4 4 500 100 50 10 Typ Max 100 20 s s s ns ns ns s s Unit
*1 : This does not include the preprogramming time. *2 : This timing is for Sector Group Protection operation. *3 : This timing is for Accelerated Program operation.
41
MBM29PL32TM/BM90/10
s ERASE AND PROGRAMMING PERFORMANCE
Limits Parameter Min Sector Erase Time Programming Time Effective Page Programming Time (Write Buffer Programming) Chip Programming Time Absolute Maximum Programming Time (16 words) Erase/Program Cycle -- -- -- -- -- 100,000 Typ 1 100 23.5 -- -- -- Max 15 3000 -- 300 6 -- s s s s ms cycle Non programming within the same page -- Excludes system-level overhead Excludes programming time prior to erasure Unit Remarks
s TSOP (1) PIN CAPACITANCE
Value Parameter Input Capacitance Output Capacitance Control Pin Capacitance RESET pin and WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Test Setup Min VIN = 0 VOUT = 0 VIN = 0 VIN = 0 -- -- -- -- Typ 8 8.5 8 20 Max 10 12 10 25 pF pF pF pF Unit
Notes : * Test conditions TA = +25C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipulated by output capacitance.
s FBGA PIN CAPACITANCE
Value Parameter Input Capacitance Output Capacitance Control Pin Capacitance RESET pin and WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Test Setup Min VIN = 0 VOUT = 0 VIN = 0 VIN = 0 -- -- -- -- Typ 8 8.5 8 15 Max 10 12 10 20 pF pF pF pF Unit
Notes : * Test conditions TA = +25C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipulated by output capacitance.
42
MBM29PL32TM/BM90/10
s SWITCHING WAVEFORMS
* Key to Switching Waveforms
WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L" Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is HighImpedance "Off" State
tRC
Address
Address Stable
tACC
CE
tOE tDF
OE
tOEH
WE
tCE tOH
Data
High-Z
Output Valid
High-Z
Read Operation Timing Diagram
43
MBM29PL32TM/BM90/10
A20 to A2 A1 to A0 (A-1)
Address Valid
Aa tRC tACC
Ab tPRC
Ac
CE
tCE
OE
tOEH
tOE tDF
WE Data High-Z
tPACC tOH Da
tPACC tOH Db tOH Dc
Page Read Operation Timing Diagram
tRC
Address
tACC
Address Stable
CE
tRH
tRP
tRH
tCE
RESET
tOH
Data
High-Z
Output Valid
Hardware Reset/Read Operation Timing Diagram 44
MBM29PL32TM/BM90/10
3rd Bus Cycle Address
555h tWC tAS PA tAH
Data Polling
PA tRC
CE
tCS tCH tCE
OE
tGHWL tWP tWPH tWHWH1 tOE
WE
tDS tDH tDF tOH
Data
A0h
PD
DQ7
DOUT
DOUT
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence.
Alternate WE Controlled Program Operation Timing Diagram
45
MBM29PL32TM/BM90/10
3rd Bus Cycle
Data Polling PA tAS tAH PA
Address
555h tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CE
tDS tDH
Data
A0h
PD
DQ 7
D OUT
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence.
Alternate CE Controlled Program Operation Timing Diagram
46
MBM29PL32TM/BM90/10
Address
555h tWC
2AAh tAS tAH
555h
555h
2AAh
SA*
SA*
CE
tCS tCH
OE
tGHWL tWP tWPH tTOW
WE
tDS AAh tDH 55h 80h AAh 55h
10h for Chip Erase 10h/ 30h tBUSY 30h
Data
RY/BY
tVCS
VCC
* : SA is the sector address for Sector Erase. Address = 555h (Word), AAAh (Byte) for Chip Erase.
Chip/Sector Erase Operation Timing Diagram
47
MBM29PL32TM/BM90/10
Address
XXXh tWC
CE
tCS tWP tCH
WE
tDS B0h tSPD
Data RY/BY
Erase Suspend Operation Timing Diagram
48
MBM29PL32TM/BM90/10
Address
VA
CE
tCH
tOE
tDF
OE
tOEH
WE
4 s tCE * DQ7 = Valid Data
DQ7
Data
DQ7
High-Z
tWHWH1 or 2
DQ6 to DQ0
Data tBUSY
DQ6 to DQ0 = Output Flag tEOE
DQ6 to DQ0 Valid Data
High-Z
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation.) Note : When checking Hardware Sequence Flags during program operations, it should be checked 4 s after issuing program command. Data Polling during Embedded Algorithm Operation Timing Diagram
49
MBM29PL32TM/BM90/10
Address
tAHT tASO tAHT tAS
CE
tCEPH
WE
4 s
tOEPH tOEH
OE
tDH tOE tCE
DQ6/DQ2
Data
tBUSY
Toggle Data
Toggle Data
Toggle Data
*
Stop
Toggling
Output Valid
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation). Note : When checking Hardware Sequence Flags during program operations, it should be checked 4 s after issuing program command. Toggle Bit l Timing Diagram during Embedded Algorithm Operations
E nter E m bedded E rasing WE
E rase S uspend E rase
E nter E rase S uspend P rogram E rase S uspend P rogram
E rase R esum e E rase S uspend R ead E rase E rase C om plete
E rase S uspend R ead
DQ6
DQ2* T oggle D Q 2 and D Q 6 w ith O E or C E
* : DQ2 is read from the erase-suspended sector. DQ2 vs. DQ6 50
MBM29PL32TM/BM90/10
CE
Rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
tBUSY
RY/BY Timing Diagram during Program/Erase Operation Timing Diagram
CE, OE
tRH
RESET
tRP tREADY
RESET Timing Diagram ( Not during Embedded Algorithms )
51
MBM29PL32TM/BM90/10
WE
RESET
tRP tRB
RY/BY
tREADY
RESET Timing Diagram ( During Embedded Algorithms )
52
MBM29PL32TM/BM90/10
A20, A19, A18, A17, A16 A15, A14, A13, A12
SGAX
SGAY
A6, A3, A2, A0
A1
VID VIH A9
tVLHT
VID VIH OE
tVLHT tWPP tVLHT tVLHT
WE
tOESP
CE
tCSP
Data
tVCS tOE
01h
VCC
SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected
Sector Group Protection Timing Diagram
53
MBM29PL32TM/BM90/10
VCC
tVCS tVIDR
tVLHT
VID VSS, VIL or VIH RESET
CE
WE
tVLHT RY/BY
Program or Erase Command Sequence
tVLHT
Unprotection period
Temporary Sector Group Unprotection Timing Diagram
54
MBM29PL32TM/BM90/10
VCC
tVCS
RESET tVLHT tVIDR Address SGAX SGAX SGAY
A6, A3, A2, A0
A1
CE
OE TIME-OUT
WE
Data
60h
60h
40h tOE
01h
60h
SGAX: Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min)
Extended Sector Group Protection Timing Diagram
55
MBM29PL32TM/BM90/10
VCC tVCS VACC ACC
tVACCR tVLHT
CE
WE tVLHT Program Command Sequence tVLHT
Acceleration period
Accelerated Program Timing Diagram
56
MBM29PL32TM/BM90/10
s FLOW CHART
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See Below)
Data Polling Embedded Program Algorithm in progress
No
Verify Data ? Yes
Increment Address
No
Last Address ? Yes
Programming Completed
Program Command Sequence (Address/Command): 555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Note : The sequence is applied for Word ( x16 ) mode. The addresses differ from Byte ( x 8 ) mode. Embedded ProgramTM Algorithm
57
MBM29PL32TM/BM90/10
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence (See Below)
Data Polling Embedded Erase Algorithm in progress
No
Data = FFh ? Yes Erasure Completed
Chip Erase Command Sequence (Address/Command): 555h/AAh
Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h Sector Address /30h Sector Address /30h Sector Address /30h
555h/10h
Additional sector erase commands are optional.
Note : The sequence is applied for Word ( x16 ) mode. The addresses differ from Byte ( x 8 ) mode.
Embedded EraseTM Algorithm
58
MBM29PL32TM/BM90/10
Start
Wait 4 s after issuing Program Command Read Byte (DQ 7 to DQ 0) Addr. = VA
DQ 7 = Data? No No DQ 5 = 1? Yes Read Byte (DQ 7 to DQ 0) Addr. = VA
Yes
VA = Valid address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = Any of the sector addresses within the sector not being protected during chip erase operation
DQ 7 = Data? * No Fail
Yes
Pass
* : DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Note : Data polling on sector-group protected sector may fail. Data Polling Algorithm
59
MBM29PL32TM/BM90/10
Start Wait 4 s after issuing Program Command Read DQ7 to DQ0 Addr. = "H" or "L" *1
Read DQ7 to DQ0 Addr. = "H" or "L"
*1
DQ6 = Toggle
No
?
Yes No DQ5 = 1? Yes *1, *2 Read DQ7 to DQ0 Addr. = "H" or "L"
Read DQ7 to DQ0 Addr. = "H" or "L"
DQ6 = Toggle ? Yes Program/Erase Operation Not Complete.Write Reset Command
No
Program/Erase Operation Complete
*1 : Read Toggle bit twice to determine whether it is toggling. *2 : Recheck Toggle bit because it may stop toggling as DQ5 changes to "1". Toggle Bit Algorithm
60
MBM29PL32TM/BM90/10
Start
Setup Sector Group Addr. (A20, A19, A18, A17, A16, A15, A14, A13, A12) PLSCNT = 1 OE = VID, A9 = VID CE = VIL, RESET = VIH A6 = A3 = A2 = A0 = VIL, A1 = VIH
Activate WE Pulse Increment PLSCNT Time out 100 s
WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group Addr. = SGA, A1 = VIH A6 = A3 = A2 = A0 = VIL Data = 01h? Yes Protect Another Sector Group? No Device Failed Remove VID from A9 Write Reset Command Yes
(
No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No
)*
Sector Group Protection Completed
* : A-1 is VIL in Byte ( x 8 ) mode.
Sector Group Protection Algorithm
61
MBM29PL32TM/BM90/10
Start
RESET = VID *1
Perform Erase or Program Operations
RESET = VIH
Temporary Sector Group Unprotection Completed *2
*1 : All protected sector groups are unprotected. *2 : All previously protected sector groups are protected.
Temporary Sector Group Unprotection Algorithm
62
MBM29PL32TM/BM90/10
Start
RESET = VID
Wait to 4 s
Device is Operating in Temporary Sector Group Unprotection Mode
No
Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h
PLSCNT = 1
To Protect Sector Group Write 60h to Sector Address
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Increment PLSCNT
Time Out 250 s Setup Next Sector Group Address
To Verify Sector Group Protection Write 40h to Sector Address (A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Read from Sector Group Address (A6 = A3 = A2 = A0 =VIL, A1 = VIH) No No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Data = 01h? Yes Yes Protection Other Sector Group? No Device Failed Remove VID from RESET Write Reset Command
Sector Group Protection Completed
Extended Sector Group Protection Algorithm
63
MBM29PL32TM/BM90/10
FAST MODE ALGORITHM
Start
555h/AAh
2AAh/55h
Set Fast Mode
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling
Verify Data? Yes No
No
In Fast Program
Increment Address
Last Address ? Yes Programming Completed
XXXh/90h Reset Fast Mode XXXh/F0h
Notes : * The sequence is applied for Word ( x16 ) mode. * The addresses differ from Byte ( x 8 ) mode.
Embedded ProgramTM Algorithm for Fast Mode
64
MBM29PL32TM/BM90/10
s ORDERING INFORMATION
Part No. MBM29PL32TM90TN MBM29PL32TM10TN MBM29PL32TM90PBT MBM29PL32TM10PBT MBM29PL32BM90TN MBM29PL32BM10TN MBM29PL32BM90PBT MBM29PL32BM10PBT Package 48-pin, plastic TSOP (1) (FPT-48P-M19) (Normal Bend) 48-ball, plastic FBGA (BGA-48P-M20) 48-pin, plastic TSOP (1) (FPT-48P-M19) (Normal Bend) 48-ball, plastic FBGA (BGA-48P-M20) Access Time (ns) 90 ns 100 ns 90 ns 100 ns 90 ns 100 ns 90 ns 100 ns Bottom Sector Top Sector Remarks
MBM29PL32TM/BM
90
TN PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP(1) Standard Pinout) PBT = 48-Ball Fine pitch Ball Grid Array Package (FBGA)
SPEED OPTION 90 = 90 ns access time 10 = 100 ns access time
DEVICE NUMBER/DESCRIPTION 32 Mbit (4M x 8/2M x 16) MirrorFlash with Page Mode, Boot Sector 3.0 V-only Read, Program, and Erase
65
MBM29PL32TM/BM90/10
s PACKAGE DIMENSIONS
48-pin plastic TSOP(1) (FPT-48P-M19) Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15(.006)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
LEAD No.
1 48
INDEX
Details of "A" part
0.25(.010)
0~8
0.600.15 (.024.006)
24
25
20.000.20 (.787.008) * 18.400.20 (.724.008)
* 12.000.20
(.472.008) 1.10 -0.05
+0.10 +.004
.043 -.002 (Mounting height)
0.50(.020)
"A"
0.10(.004)
0.17 -0.08 .007 -.003
C
+0.03 +.001
0.100.05 (.004.002) (Stand off height) 0.220.05 (.009.002) 0.10(.004)
M
2003 FUJITSU LIMITED F48029S-c-6-7
Dimensions in mm (inches) Note : The values in parentheses are reference values.
(Continued)
66
MBM29PL32TM/BM90/10
(Continued) 48-ball plastic FBGA (BGA-48P-M20)
8.000.20(.315.008) 1.08 -0.13 .043 -.005 (Mounting height) 0.380.10(.015.004) (Stand off)
+0.12 +.003
5.60(.220) 0.80(.031)TYP
6 5 6.000.20 (.236.008) 4 4.00(.157) 3 2 1
(INDEX AREA)
H
G
F
E
D
C
B
A
M
48-o0.450.05 (48-o.018.002)
o0.08(.003)
0.10(.004)
C
2003 FUJITSU LIMITED B48020S-c-2-2
Dimensions in mm (inches) Note : The values in parentheses are reference values.
67
MBM29PL32TM/BM90/10
FUJITSU LIMITED
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F0407 (c) FUJITSU LIMITED Printed in Japan

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